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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xrt91l30 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver december 2006 rev. 1.0.1 general description the xrt91l30 is a fully integrated sonet/sdh transceiver for sonet/sdh 622.08 mbps sts-12/ stm-4 or 155.52 mbps sts-3/stm-1 applications. the transceiver includes an on-chip clock multiplier unit (cmu), which uses a high frequency phase- locked loop (pll) to generate the high-speed transmit serial clock from a slower external clock reference. it also provides clock and data recovery (cdr) function by synchronizing its on-chip voltage controlled oscillator (vco) to the incoming serial data stream. the internal cdr unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. either the internally recovered clock or the externally recovered clock can be used for loop timing applications. the chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide lvttl system interface in both receive and transmit directions. the transmit section includes an option to accept a parallel clock signal from the framer/mapper to synchronize the transmit section timing. the device can internally monitor loss of signal (los) condition and automatically mute received data upon los. an on-chip sonet/sdh frame byte and boundary detector and frame pulse generator offers the ability recover sonet/sdh framing and to byte align the receive serial data stream into the 8-bit parallel bus. applications ? sonet/sdh-based transmission systems ? add/drop multiplexers ? cross connect equipment ? atm and multi-service switches, routers and switch/routers ? dslams ? sonet/sdh test equipment ? dwdm termination equipment f igure 1. b lock d iagram of xrt91l30 reset dloop rloops looptime losext sts-12/sts-3 aloop dlosdis framepulse oof clock control control block cdrdis cdrrefsel cmufreqsel sts-12/stm-4 or sts-3/stm-1 transceiver loop filters cap1p cap2p cap1n cap2n rxdo[7:0] rxpclko cdr rxip/n 8 div by 8 xrxclkip/n sipo (serial input parallel output) mux piso (parallel input serial output) dloop aloop rloops re-timer cmu txop/n mux xor ttlrefclk refclkp/n cdrauxrefclk mux txpclk_io pio_ctrl div by 8 enb enb txdi[7:0] 8 mux
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 2 features ? targeted for sonet sts-12/sts-3 and sdh stm-4/stm-1 applications ? selectable full duplex operation between sts-12/stm-4 standard rate of 622.08 mbps or sts-3/stm-1 155.52 mbps ? single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (cmu), serial- to-parallel converter, clock data recovery (cdr) functions, and a sonet/sdh frame and byte boundary detection circuit ? ability to disable and bypass onchip cdr for external based received reference clock recovery thru differential lvpecl input pins xrxclkip/n ? 8-bit lvttl parallel data bus paths running at 77.76 mbps in sts-12/stm-4 or 19.44 mbps in sts-3/stm-1 mode of operation ? uses differential lvpecl or single-ended lvttl cmu reference clock frequencies of either 19.44 mhz or 77.76 mhz for both sts-12/stm-1 or sts-3/stm-1 operations ? optional use of 77.76 mhz single-ended lvttl input for independent cdr reference clock operation ? able to detect and recover sonet/sdh frame boundary and byte align received data on the parallel bus ? diagnostics features include los monitoring and automatic received data mute upon los ? provides local, remote and split loop-back modes as well as loop timing mode ? optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the transceiver transmit timing. ? meets telcordia, ansi and itu-t g.783 and g.825 sdh jitter requirements including t1.105.03 - 2002 sonet jitter tolerance specification, bellcore tr-nwt-000253 and gr-253-core, gr-253 ilr sonet jitter specifications. ? complies with ansi/tia/eia-644 and ieee p1596.3 3.3v lvds standard, 3.3v lvpecl, and jesd 8-b lvttl and lvcmos standard. ? operates at 3.3v core with 3.3v i/o ? less than 660mw in sts-3/stm-1 mode or 800mw in sts-12/stm-4 mode typical power dissipation ? package: 10 x 10 x 2.0 mm 64-pin qfp
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 3 f igure 2. 64 qfp p in o ut of the xrt91l30 (t op v iew ) xrt91l30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 reset looptm_noja cmufreqsel vdd_pecl txop txon losddis extrxclkip extrxclkin vdd_pecl oof cdrdis rxip rxin vdd3.3 refclkp agnd fl_2 sts1_2 dja_2/cs mclk_2 gnd rclk_2 vdd rneg_2 rpos_2 gnd dja_0/sclk ds3/e3_0 sts1_0 fl0 agnd avdd gnd rrclk_1 rrpos_1 rrneg_1 rclkes nc vdd ds3/e3_2 sdo fss rrneg_2 rrpos_2 rrclk_2 gnd avdd agnd fl1 sts1_1 mclk_1 gnd rclk_1 rpos_1 rneg_1 vdd rneg_0 rpos_0 rclk_0 gnd mclk_0 dja_1/sdi agnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 xrt91l30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 reset looptime cmufreqsel vdd_pecl txop txon dlosdis xrxclkip xrxclkin vdd_pecl oof cdrdis rxip rxin vdd3.3 refclkp cdrauxrefclk vdd3.3 framepulse rxpclko gnd rxdo7 rxdo6 rxdo5 rxdo4 rxdo3 rxdo2 gnd rxdo1 rxdo0 vdd3.3 refclkn pio_ctrl vdd3.3 gnd gnd agnd_rx avdd3.3_rx cap2p cap2n cap1n cap1p avdd3.3_tx agnd_tx ttlrefclk gnd vdd3.3 losext txpclk_io txdi7 txdi6 gnd txdi5 txdi4 txdi3 txdi2 txdi1 txdi0 sts12/sts3 cdrrefsel vdd3.3 dloop rloops aloop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ordering information p art n umber p ackage o perating t emperature r ange xrt91l30iq 64 pin lead qfp -40 c to +85 c
xrt91l30 xr rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver i table of contents general description .................................................................................................1 applications ................................................................................................................... ........................1 f igure 1. b lock d iagram of xrt91l30 ...................................................................................................................... ................ 1 features ............................................................................................................................... .......................2 f igure 2. 64 qfp p in o ut of the xrt91l30 (t op v iew )............................................................................................................ 3 ordering information........................................................................................................... ..........3 t able of c ontents ............................................................................................................ i pin descriptions ..........................................................................................................4 ............................................................................................................................... ......................................4 h ardware c ontrol ............................................................................................................................... .....4 t ransmitter s ection ............................................................................................................................... ...7 r eceiver s ection ............................................................................................................................... .........9 p ower and g round ............................................................................................................................... ...10 1.0 functional description .................................................................................................. ...........12 1.1 sts-12/stm-4 and sts-3/stm-1 mode of operation ......................................................................... 12 1.2 clock input reference for clock multiplier (synthesizer) unit ...................................... 12 t able 1: cmu r eference f requency o ptions (d ifferential or s ingle -e nded ) ................................................................... 12 1.3 data latency ............................................................................................................ ................................. 12 t able 2: d ata ingress to data egress latency ....................................................................................................................... 12 2.0 receive section ......................................................................................................... ....................13 2.1 receive serial input .................................................................................................... ........................... 13 f igure 3. r eceive s erial i nput i nterface b lock ..................................................................................................................... 13 2.2 recieve serial data input timing ........................................................................................ .............. 14 f igure 4. r eceive h igh -s peed s erial d ata i nput t iming d iagram .......................................................................................... 14 t able 3: r eceive h igh - speed s erial d ata i nput t iming (sts-12/stm-4 o peration ) ............................................................. 14 t able 4: r eceive h igh -s peed s erial d ata i nput t iming (sts-3/stm-1 o peration )............................................................... 14 2.3 receive clock and data recovery ......................................................................................... ......... 15 t able 5: c lock d ata r ecovery unit reference clock settings ............................................................................................ 15 t able 6: c lock and d ata r ecovery u nit p erformance .......................................................................................................... 15 2.3.1 internal clock and data recovery bypass ................................................................................ ............ 16 f igure 5. i nternal c lock and d ata r ecovery b ypass ............................................................................................................ 16 2.4 external receive loop filter capacitors ................................................................................. .. 16 f igure 6. e xternal l oop f ilters ............................................................................................................................... ............... 16 2.5 loss of signal .......................................................................................................... ................................ 16 f igure 7. los d eclaration circuit ............................................................................................................................... ............ 17 2.6 sonet frame boundary detection and by te alignment recovery .................................... 17 2.7 receive serial input to parallel outp ut (sipo) ......................................................................... 17 f igure 8. s implified b lock d iagram of sipo .......................................................................................................................... .18 2.8 receive parallel output interface ....................................................................................... ........ 18 f igure 9. r eceive p arallel o utput i nterface b lock ............................................................................................................. 18 2.9 disable parallel receive data output upon los ..................................................................... 18 2.10 receive parallel data output timing .................................................................................... ...... 19 f igure 10. r eceive p arallel o utput t iming ............................................................................................................................ 19 t able 7: r eceive p arallel d ata o utput t iming (sts-12/stm-4 o peration ) ......................................................................... 19 t able 8: r eceive p arallel d ata o utput t iming (sts-3/stm-1 o peration ) ........................................................................... 19 t able 9: pecl and ttl r eceive o utputs t iming s pecification .............................................................................................. 20 3.0 transmit section ........................................................................................................ ..................21 3.1 transmit parallel input interf ace ....................................................................................... .......... 21 f igure 11. t ransmit p arallel i nput i nterface b lock ............................................................................................................. 21 3.2 transmit parallel data input timing ..................................................................................... ......... 22 f igure 12. t ransmit p arallel i nput t iming .............................................................................................................................. 2 2 t able 10: t ransmit p arallel d ata i nput t iming (sts-12/stm-4 o peration )......................................................................... 22 t able 11: t ransmit p arallel d ata i nput t iming (sts-3/stm-1 o peration )........................................................................... 22 3.3 alternate transmit parallel bus clo ck input option .......................................................... 23 f igure 13. a lternate t ransmit p arallel i nput i nterface b lock (p arallel c lock i nput o ption ) ...................................... 23 3.4 alternate transmit parallel data inpu t timing ....................................................................... 23 f igure 14. a lternate t ransmit p arallel i nput t iming ............................................................................................................ 23 t able 12: a lternate t ransmit p arallel d ata i nput t iming (sts-12/stm-4 o peration ) ...................................................... 24 t able 13: a lternate t ransmit p arallel d ata i nput t iming (sts-3/stm-1 o peration ). ....................................................... 24
xr xrt91l30 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 ii 3.5 transmit parallel input to serial outp ut (piso) ...................................................................... 24 f igure 15. s implified b lock d iagram of piso ......................................................................................................................... 2 4 3.6 clock multiplier unit (cmu) and re-timer ................................................................................ ..... 25 t able 14: c lock m ultiplier u nit p erformance ....................................................................................................................... 25 3.7 loop timing and clock control ........................................................................................... ............ 25 t able 15: l oop t iming and c lock r ecovery configurations ................................................................................................. 26 f igure 16. l oop t iming m ode u sing i nternal cdr or an e xternal r ecovered c lock ....................................................... 26 3.8 transmit serial output control .......................................................................................... ........... 27 f igure 17. t ransmit s erial o utput i nterface block .............................................................................................................. 27 4.0 diagnostic features ..................................................................................................... .............. 28 4.1 serial remote loopback .................................................................................................. ................... 28 f igure 18. s erial r emote l oopback ............................................................................................................................... .......... 28 4.2 digital local loopback .................................................................................................. ..................... 28 f igure 19. d igital l ocal l oopback ............................................................................................................................... ............ 28 4.3 analog local loopback ................................................................................................... ................... 29 f igure 20. a nalog l ocal l oopback ............................................................................................................................... ........... 29 4.4 split loopback .......................................................................................................... ............................... 29 f igure 21. s plit l oopback ............................................................................................................................... .......................... 29 4.5 eye diagram ............................................................................................................. .................................. 30 f igure 22. t ransmit e lectrical o utput e ye d iagram ............................................................................................................. 30 4.6 sonet jitter requirements ............................................................................................... .................. 30 4.6.1 jitter tolerance: ...................................................................................................... .......................................... 30 f igure 23. gr-253 j itter t olerance m ask .............................................................................................................................. 3 1 t able 16: xrt91l30 r eceiver j itter t olerance p erformance ............................................................................................. 31 f igure 24. xrt91l30 m easured j itter t olerance with 77.76mh z r eference c lock ......................................................... 31 f igure 25. xrt91l30 m easured j itter t olerance with 19.44mh z r eference c lock ......................................................... 32 4.6.2 jitter generation...................................................................................................... .......................................... 32 t able 17: xrt91l30 o ptical j itter g eneration using 223-1 prbs pattern ........................................................................ 32 t able 18: xrt91l30 o ptical j itter g eneration using 223-1 prbs pattern using n on - standard f ilters ........................ 32 5.0 electrical characteristics .............................................................................................. ..... 33 a bsolute m aximum ratings .................................................................................................................. 33 absolute maximum power and input/output ratings ......................................................... 33 power and current dc e lectrical c haracteristics .................................................................... 33 ............................................................................................................................... .................................... 33 lvpecl and lvttl logic signal dc electrical characteristics...................................... 34 ordering information ........................................................................................................... ....... 35 package dimensions ................................................................................................ 35 r evision h istory ............................................................................................................................... ....... 36
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 4 pin descriptions hardware control n ame l evel t ype p in d escription reset lvttl, lvcmos i 1 master reset input active "high." when this pin is pulled "high" , the internal state machines are set to their default state. "low" = normal operation "high" = master hardware reset (100ns minimum) sts12/ sts3 lvttl, lvcmos i 59 data rate selection selects sonet/sdh transmission and reception speed rate "low" = sts-3/stm-1 155.52 mbps "high" = sts-12/stm-4 622.08 mbps cmufreqsel lvttl, lvcmos i 3 clock multiplier unit reference frequency select this pin is used to select the frequency of the refclkp/n or ttlrefclk input to the cmu. "low" = 77.76 mhz reference clock "high" = 19.44 mhz reference clock n ote : refclkp/n or ttlrefclk input should be generated from an lvpecl/lvttl crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for sonet systems.. cmu- freqsel sts12/ sts3 refclkp/n or ttlrefclk reference frequency d ata r ate 00 77.76 mhz sts-3/stm-1 155.52 mbps 0 1 77.76 mhz sts-12/stm-4 622.08 mbps 10 19.44 mhz sts-3/stm-1 155.52 mbps 1 1 19.44 mhz sts-12/stm-4 622.08 mbps
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 5 cdrrefsel lvttl, lvcmos i 60 clock and data recover unit reference frequency select selects the clock and data recovery unit reference frequency based on the table below. "low" = cdr uses cmu?s reference clock "high" = cdr reference clock from cdrauxrefclk n ote : cdrauxrefclk requires accuracy of 77.76 mhz +/- 500ppm. looptime lvttl, lvcmos i 2 loop timing mode when the loop timing mode is activated the external reference clock to the input of the retimer is replaced with the high-speed recovered receive clock from the cdr. "low" = disabled "high" = loop timing activated cdrdis lvttl, lvcmos i 12 clock and data recovery unit disable active "high." disables internal clock and data recovery unit. received serial data bypasses the integrated cdr block. rxinp/n is then sampled on the rising edge of externally recovered differential clock xrxclkip/n coming from the opti - cal module. "low" = internal cdr unit is enabled "high" = internal cdr unit is disabled and bypassed pio_ctrl lvttl, lvcmos i 48 transmit parallel clock directional control transmit parallel clock output operation if this pin is asserted "high", txpclk_io is a parallel bus clock output. data on the txdi[7:0] must be synchronously applied prior to the sampling by the piso at the rising edge of txpclk_io clock output driven by the xrt91l30. alternate transmit parallel clock input operation asserting this control pin "low" or if left unconnected, it config - ures txpclk_io to serve as a parallel bus clock input rather than a parallel bus clock output and permits the xrt91l30 to accept the external clock input. data on the txdi[7:0] is then sampled at the rising edge of the txpclk_io clock input driven by the framer/mapper device. "low" = txpclk_io is a parallel clock input. "high" = txpclk_io is a parallel clock output. n ote : parallel clock input operation has the advantage of permitting the framer/mapper device timing to be synchronized with the transceiver transmitter timing. this pin is provided with an internal pull-down. n ame l evel t ype p in d escription cdrrefsel sts12/ sts3 cdrauxrefclk f requency d ata r ate 0 cdr uses cmu?s reference clock (see cmufreqsel pin) 10 77.76 mhz sts-3/stm-1 155.52 mbps 11 77.76 mhz sts-12/stm-4 622.08 mbps
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 6 rloops lvttl, lvcmos i 63 serial remote loopback the serial remote loopback mode interconnects the receive serial data input to the transmit serial data output. if serial remote loopback is enabled, the 8-bit parallel transmit data input is ignored while the 8-bit parallel receive data output is maintained. "low" = disabled "high" = serial remote loopback mode enabled n ote : dloop and rloops can be enabled simultaneously to achieve a split loopback diagnostic feature in normal operation. dloop lvttl, lvcmos i 62 digital local loopback the digital local loopback mode interconnects the 8-bit parallel transmit data input and txclk to the 8-bit parallel receive data output and rxclk respectively while maintaining the transmit serial data output. if digital local loopback is enabled, the receive serial data input is ignored. "low" = disabled "high" = digital local loopback mode enabled n ote : dloop and rloops can be enabled simultaneously to achieve a split loopback diagnostic feature in normal operation. aloop lvttl, lvcmos i 64 analog local loopback this loopback feature serializes the 8-bit parallel transmit data input and presents the data to the transmit serial output and in addition it also internally routes the serialized data back to the clock and data recovery block for serial to parallel conversion. the received serial data input is ignored. "low" = disabled "high" = analog local loopback mode enabled n ame l evel t ype p in d escription
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 7 transmitter section n ame l evel t ype p in d escription txdi0 txdi1 txdi2 txdi3 txdi4 txdi5 txdi6 txdi7 lvttl, lvcmos i 58 57 56 55 54 53 51 50 transmit parallel data input transmit parallel clock output operation the 77.76 mbps (sts-12/stm-4) / 19.44 mbps (sts-3/stm-1) 8-bit parallel transmit data should be applied to the transmit parallel bus and simultaneously referenced to the rising edge of the txpclk_io clock output. the 8-bit parallel interface is mul - tiplexed into the transmit serial output interface with the msb first (txdi[7:0]). alternate transmit parallel clock input operation when operating is this mode, txpclk_io is no longer a paral - lel clock output reference but reverses direction and serves as the parallel transmit clock input reference for the piso (parallel input to serial output) block. the 77.76 mbps (sts-12/stm-4) / 19.44 mbps (sts-3/stm-1) 8-bit parallel transmit data should be applied to the transmit parallel bus and simultaneously refer - enced to the rising edge of the txpclk_io clock input. txop txon lvpecl diff o 5 6 transmit serial data output the transmit serial data stream is generated by multiplexing the 8-bit parallel transmit data input into a 622.08 mbps sts-12/ stm-4 or 155.52 mbps sts-3/stm-1 serial data stream. txpclk_io lvttl, lvcmos i/o 49 transmit parallel clock input/output (77.76/19.44 mhz) transmit parallel clock output operation when the pio_ctrl pin 48 is asserted "high," this pin will out - put a 77.76 mhz (sts-12/stm-4) or 19.44 mhz (sts-3/stm- 1) clock output reference for the 8-bit parallel transmit data input txdi[7:0]. this clock is used by the framer/mapper device to present the txdi[7:0] data which the xrt91l30 will latch on the rising edge of this clock. this enables the framer/mapper device and the xrt91l30 transceiver to be in synchronization. alternate transmit parallel clock input operation when the pio_ctrl pin 48 is asserted "low," this pin will accept a 77.76 mhz (sts-12/stm-4) or 19.44 mhz (sts-3/ stm-1) clock input reference for the 8-bit parallel transmit data input txdi[7:0]. the xrt91l30 will latch data at txdi[7:0] on the rising edge of this clock. this has the enormous advantage of enabling the framer/mapper device transmit timing to be syn - chronized with the transceiver transmit timing.
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 8 refclkp refclkn lvpecl diff i 16 17 reference clock input (77.76 mhz or 19.44 mhz) this differential clock input reference is used for the transmit clock multiplier unit (cmu) and clock data recovery (cdr) to provide the necessary high speed clock reference for this device. it will accept either a 77.76 mhz or a 19.44 mhz differ - ential lvpecl clock source. pin cmufreqsel determines the value used as the reference. see pin cmufreqsel for more details. refclkp/n inputs are internally biased to 1.65v. n ote : in the event that ttlrefclk lvttl input is used instead of these differential inputs for clock reference, the refclkp should be tied to ground. ttlrefclk lvttl, lvcmos i 36 ttl reference clock input (77.76 mhz or 19.44 mhz) this optional lvttl clock input reference is used for the trans - mit clock multiplier unit (cmu) and clock data recovery (cdr) to provide the necessary high speed clock reference for this device rather than a differential clock source. it will accept either a 77.76 mhz or a 19.44 mhz lvttl clock source. pin cmufreqsel determines the value used as the reference. see pin cmufreqsel for more details. n ote : in the event that refclkp/n differential inputs are used instead of this lvttl input for clock reference, the ttlrefclk should be tied to ground. transmitter section n ame l evel t ype p in d escription
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 9 receiver section n ame l evel t ype p in d escription rxdo0 rxdo1 rxdo2 rxdo3 rxdo4 rxdo5 rxdo6 rxdo7 lvttl, lvcmos o 19 20 22 23 24 25 26 27 receive parallel data output 77.76 mbps (sts-12/stm-4) / 19.44 mbps (sts-3/stm-1) 8-bit parallel receive data output is updated simultaneously on the falling edge of the rxpclko output. the 8-bit parallel interface is de-multiplexed from the receive serial data input msb first (rxdo[7]). the xrt91l30 will output the data on the falling edge of rxpclko clock. rxip rxin diff lvpecl i 13 14 receive serial data input the differential receive serial data stream of 622.08 mbps sts-12/stm-1 or 155.52 mbps sts-3/stm-1 is applied to these input pins. xrxclkip xrxclkin diff lvpecl i 8 9 external recovered receive clock input the differential receive serial data stream of 622.08 mbps sts-12/stm-1 or 155.52 mbps sts-3/stm-1 is sampled on the rising edge of this externally recovered differential clock coming from the optical module. it is used when the internal cdr unit is disabled and bypassed by the cdrdis pin. n ote : in the event that xrxclkip/n differential input pins are unused, xrxclkip should be tied to vcc with a 1k ohm pull-up and xrxclkin should be tied to ground with a 1k ohm pull-down. rxpclko lvttl, lvcmos o 29 receive parallel clock output (77.76 mhz or 19.44 mhz) 77.76 mhz (sts-12/stm-4) or 19.44 mhz (sts-3/stm-1) clock output reference for the 8-bit parallel receive data output rxdo[7:0]. the parallel received data output bus will be updated on the falling edge of this clock. cdraux- refclk lvttl, lvcmos i 32 clock and data recovery auxillary reference clock 77.76 mhz 500 ppm auxillary reference clock for the cdr. n ote : in the event that cdrauxrefclk lvttl input pin is unused, cdrauxrefclk should be tied to ground. oof lvttl, lvcmos i 11 out of frame input indicator this level sensitive input pin is used to initiate frame detection and byte alignment recovery when oof is declared by the downstream device. when this pin is held high, frame - pulse will pulse for a single rxpclko period upon the detec - tion of every third frame alignment a2 byte in the incoming sonet/sdh frame. "low" = normal operation "high" = oof indication initiating frame detection and byte boundary recovery and activating framepulse framepulse lvttl, lvcmos o 30 sonet frame alignment pulse this pin will generate a single pulse for an rxpclko clock period upon the detection of the third frame alignment a2 byte whenever the oof input pin is held high. the parallel received data output bus will then be byte aligned to this newly recov - ered sonet/sdh frame.
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 10 power and ground cap1p cap2p analog - 39 42 cdr non-polarized external filter capacitor c1 = 0.47 f 10% tolerance (isolate from noise and place close to pin) cap1n cap2n analog - 40 41 cdr non-polarized external filter capacitor c2 = 0.47 f 10% tolerance (isolate from noise and place close to pin) dlosdis lvttl, lvcmos i 7 los (los of signal) detect disable disables internal los monitoring and automatic muting of rxdo[7:0] upon los detection (according to gating shown in figure 7). los is declared when a string of 128 consecutive zeros occur on the line. los condition is cleared when the 16 or more pulse transitions is detected for 128 bit period sliding window. "low" = monitor and mute received data upon los declaration "high" = disable los monitoring (see figure 7 for logical oper - ation). losext se-lvpecl i 33 los or signal detect input from optical module active "low." when active, this pin can force the received data output bus rxdo[7:0] to a logic state of ?0? per figure 7 . "low" = forced los "high" = normal operation n ame t ype p in d escription vdd3.3 pwr 15, 18, 31, 34, 47, 61 3.3v cmos power supply vdd3.3 should be isolated from the analog vdd power supplies. use a ferrite bead along with an internal power plane separation. the vdd3.3 power supply pins should have bypass capacitors to the nearest ground. for best results, refer to application notes about board layout guidelines. avdd3.3_tx pwr 38 analog 3.3v transmitter power supply avdd3.3_tx should be isolated from the digital power supplies. for best results, use a ferrite bead along with an internal power plane separation. the avdd3.3_tx power supply pins should have bypass capacitors to the nearest ground. avdd3.3_rx pwr 43 analog 3.3v receiver power supply avdd3.3_rx should be isolated from the digital power supplies. for best results, use a ferrite bead along with an internal power plane separation. the avdd3.3_rx power supply pins should have bypass capacitors to the nearest ground. vdd_pecl pwr 4, 10 3.3v input/output lvpecl bus power supply these pins require a 3.3v potential voltage for properly biasing the differential lvpecl input and output pins. agnd_tx pwr 37 transmitter analog ground for 3.3v analog power supplies it is recommended that all ground pins of this device be tied together. n ame l evel t ype p in d escription
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 11 agnd_rx pwr 44 receiver analog ground for 3.3v analog power supplies it is recommended that all ground pins of this device be tied together. gnd gnd 21, 28, 35, 45, 46, 52 power supply and thermal ground it is recommended that all ground pins of this device be tied together. n ame t ype p in d escription
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 12 1.0 functional description the xrt91l30 transceiver is designed to operate with a sonet framer/asic device and provide a high- speed serial interface to optical networks. the transceiver converts 8-bit parallel data running at 77.76 mbps (sts-12/stm-4) or 19.44 mbps (sts-3/stm-1) to a serial differential lvpecl bit stream at 622.08 mbps or 155.52 mbps and vice-versa. it implements a clock multiplier unit (cmu), sonet/sdh serialization/de- serialization (serdes), receive clock and data recovery (cdr) unit and a sonet/sdh frame and byte boundary detection circuit. the transceiver is divided into transmit and receive sections and is used to provide the front end component of sonet equipment, which includes primarily serial transmit and receive functions. 1.1 sts-12/stm-4 and sts-3/stm-1 mode of operation functionality of the transceiver can be configured by using the appropriate signal level on the sts-12/ sts-3 pin. sts-3/stm-1 mode is selected by pulling sts-12/ sts-3 "low" as described in the hardware pin descriptions. however, if sts-12/stm-4 mode is desired, it is selected by pulling sts-12/ sts-3 "high." therefore, the following sections describe the functionality rather than how each function is controlled. hence, the hardware pin and register bit descriptions focus on device configuration. 1.2 clock input reference for clock multiplier (synthesizer) unit the xrt91l30 can accept both a 19.44 mhz or a 77.76 mhz differential lvpecl clock input at refclkp/n or a single-ended lvttl clock at ttlrefclk as its internal timing reference for generating higher speed clocks. the refclkp/n or ttlrefclk input should be generated from an lvpecl/lvttl crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for sonet systems. the reference clock can be provided with one of two frequencies chosen by cmufreqsel. the reference frequency options for the xrt91l30 are listed in ta b l e 1. 1.3 data latency due to different operating modes and data logic paths through the device, there is an associated latency from data ingress to data egress. ta b l e 2 specifies the data latency for a typical path. t able 2: d ata ingress to data egress latency t able 1: cmu r eference f requency o ptions (d ifferential or s ingle -e nded ) cmufreqsel sts12/sts3 refclkp/n or ttlrefclk reference frequency d ata r ate 0 0 77.76 mhz sts-3/stm-1 155.52 mbps 0 1 77.76 mhz sts-12/stm-4 622.08 mbps 1 0 19.44 mhz sts-3/stm-1 155.52 mbps 1 1 19.44 mhz sts-12/stm-4 622.08 mbps m ode o f o peration d ata p ath c lock r eference r ange o f c lock c ycles thru-mode msb at rxip/n to data on rxdo[7:0] recoved rxip/n clock 25 to 35 serial remote loopback msb at rxip/n to msb at txop/n recoved rxip/n clock 2 to 4
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 13 2.0 receive section the receive section of xrt91l30 include the inputs rxip/n, followed by the clock and data recovery unit (cdr) and receive serial-to-parallel converter. the rece iver accepts the high speed non-return to zero (nrz) serial data at 622.08 mbps or 155.52 mbps through the input interfaces rxip/n. the clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled nrz data stream. the recovered serial data is converted into an 8-bit-wide, 77.76 mbps or 19.44 mbps parallel data and presented to the rxdo[7:0] parallel interface. this parallel interface is designed for single-ended lvttl operation. a divide- by-8 version of the high-speed recovered clock rxpclkop/n, is used to synchronize the transfer of the 8-bit rxdo[7:0] data with the receive portion of the framer/mapper device. upon initialization or loss of signal or loss of lock, the external reference clock signal of 19.44 mhz or 77.76 mhz is used to start-up the clock recovery phase-locked loop for proper operation. in certain applications, the cdr block on the xrt91l30 can be disabled and bypassed by enabling the cdrdis pin to permit the flexibility of using an externally recovered receive clock thru the xrxclkip/n pins. 2.1 receive serial input the receive serial inputs are applied to rxip/n. the receive serial inputs can be ac or dc coupled to an optical module or an electrical interface. a simplified dc coupling block diagram is shown in figure 3 . (for ac- coupled applications, refer to application note tan-9130.) n ote : some optical modules integrate ac coupling capacitors within the module. ac or dc coupling is largely specific to system design and optical module of choice. f igure 3. r eceive s erial i nput i nterface b lock optical module rxip rxin optical fibe r xrt91l30 sts-12/stm-4 or sts-3/stm-1 transceiver 120 82 xrxclkip xrxclkin (optional) 1k 1k install terminators as close to rxip and rxin pins tie unused differential input pins to vcc and gnd
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 14 2.2 recieve serial data input timing the received high-speed serial differential data input must adhere to the set-up and hold time timing specifications below. t able 4: r eceive h igh -s peed s erial d ata i nput t iming (sts-3/stm-1 o peration ) f igure 4. r eceive h igh -s peed s erial d ata i nput t iming d iagram t able 3: r eceive h igh - speed s erial d ata i nput t iming (sts-12/stm-4 o peration ) s ymbol p arameter m in t yp m ax u nits t rxclk receive external recovered clock period 1.608 ns t rx_su serial data setup time with respect to xrxclkip/n 400 ps t rx_hd serial data hold time with respect to xrxclkip/n 100 ps s ymbol p arameter m in t yp m ax u nits t rxclk receive external recovered clock period 6.43 ns t rx_su serial data setup time with respect to xrxclkip/n 1.5 ns t rx_hd serial data hold time with respect to xrxclkip/n 1.5 ns t rxclk rxip rxin xrxclkip xrxclkin t rx_hd t rx_su
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 15 2.3 receive clock and data recovery the clock and data recovery (cdr) unit accepts the high speed nrz serial data from the differential lvpecl receiver and generates a clock that is the same frequency as the incoming data. the clock recovery can either utilize the transmitter?s cmu reference clock from either refclkp/n or ttlrefclk or it can use independent clock source cdrauxrefclk to train and monitor its clock recovery pll. initially upon startup, the pll locks to the local reference clock within 500 ppm. once this is achieved, the pll then attempts to lock onto the incoming receive data stream. whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery pll will switch and lock back onto the local reference clock. whenever a loss of lock or a loss of signal event occurs, the cdr will continue to supply a receive clock (based on the local reference) to the framer/mapper device. when the losext is asserted by the optical module or when los is detected, the receive parallel data output will be forced to a logic zero state for the entire duration that a los condition is detected. this acts as a receive data mute upon los function to prevent random noise from being misinterpreted as valid incoming data. when the losext becomes inactive and the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source and los is no longer declared, the clock recovery pll will switch and lock back onto the incoming receive data stream. table 5 shows clock and data recovery reference clock settings. ta b l e 6 specifies the clock and data recovery unit performance characteristics. t able 5: c lock d ata r ecovery unit reference clock settings 1 requires frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for sonet systems. 2 cdrauxrefclk requires accuracy of 77.76 mhz +/- 200ppm. t able 6: c lock and d ata r ecovery u nit p erformance cmufreqsel cdrrefsel sts12/ sts3 refclkp/n 1 or ttlrefclk 1 f requency (mh z ) cdrauxrefclk 2 f requency (mh z ) cdr o utput f requency (mh z ) 0 0 0 77.76 mhz not used 155.52 0 0 1 77.76 mhz not used 622.08 1 0 0 19.44 mhz not used 155.52 1 0 1 19.44 mhz not used 622.08 x 1 0 not referenced by cdr 77.76 mhz 155.52 x 1 1 not referenced by cdr 77.76 mhz 622.08 n ame p arameter m in t yp m ax u nits ref duty reference clock duty cycle 40 60 % ref tol reference clock frequency tolerance -200 +200 ppm
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 16 2.3.1 internal clock and data recovery bypass optionally, the internal cdr unit can be disabled and bypassed in lieu of an externally recovered clock. asserting the cdrdis "high" disables the internal clock and data recovery unit and the received serial data bypasses the integrated cdr block. rxinp/n is then sampled on the rising edge of the externally recovered differential clock xrxclkip/n coming from the optical module or an external clock recovery unit. figure 5 shows the possible internal paths of the recovered clock and data. 2.4 external receive loop filter capacitors these 0.47 f non-polarized external loop filter capacitors provide the necessary components to achieve the required receiver jitter performance. they must be well isolated to prohibit noise entering the cdr block and should be placed as close to the pins as much as possible. figure 6 shows the pin connections and external loop filter components. these two non-polarized capacitors should be of +/- 10% tolerance. 2.5 loss of signal xrt91l30 supports internal loss of signal detection (los) and external los detection. the internal loss of signal detector monitors the incoming data stream and if the incoming data stream has no transition continuously for more than 128 bit periods, loss of signal is declared. this los detection will be removed when the circuit detects 16 transitions in a 128 bit period sliding window. pulling the corresponding dlosdis signal to a high level will disable the internal los detection circuit. the external los function is supported by the losext input. the single-ended lvpecl input usually comes from the optical module through an output usually called ?sd? or ?flag? which indicates the lack or presence of optical power. depending on the manufacturer of these devices the polarity of this signal can be either active "low" or active "high." losext is an active "low" signal requiring a low level to assert or invoke a forced los. the external losext input pin and internal los detector are gated to control detection and declaration of loss of signal (see figure 7). whenever los is internally detected or an external los is asserted thru the losext pin, the xrt91l30 will automatically force the receive parallel data output to a logic state "0" for the entire duration that a los f igure 5. i nternal c lock and d ata r ecovery b ypass f igure 6. e xternal l oop f ilters rxip rxin mux cdr mux cdrdis clk data xrxclkip xrxclkin data clock sipo div by 8 clock parallel data 8 cap2n cap1n 0.47uf non-polarized cap2p cap1p 0.47uf non-polarized pin 42 pin 39 pin 40 pin 41
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 17 condition is declared. this acts as a receive data mute upon los function to prevent random noise from being misinterpreted as valid incoming data. 2.6 sonet frame boundary detection and byte alignment recovery a frame and byte boundary detection circuit searches the incoming data channel for three consecutive a1 (0xf6 hex) bytes followed by three consecutive a2 (0x28 hex) bytes. the detector operates under the control of the oof (out of frame) signals provided from the sonet framer. detection is enabled when oof is held "high" and remains active until oof goes "low." when framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming receive data stream. the receive serial-to- parallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for output on the parallel data output bus rxdo[7:0]. the frame boundary is reported on the frame pulse (framepulse) output at the onset of detecting the third a2 byte pattern when any serial 48-bit pattern matching the framing pattern is detected on the incoming data stream. while in the pattern search and detection state and so long is oof is active, the frame pulse (framepulse) output is activated for one byte clock cycle (rxpclko = 12.86 ns pulse duration for sts-12/stm-4 or 51.44 ns pulse duration for sts-3/ stm-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. once the sonet framer overhead circuitry has verified that frame and byte synchronization are correct, the oof input pin should be de-asserted by the sonet framer to disable the xrt91l30 frame search process from trying to synchronize repeatedly and to de-activate framepulse. when the xrt91l30?s framing pattern detection is disabled upon the de-assertion of oof input pin from the sonet framer, the byte boundary will lock to the detected location and will remain locked to that location found when detection was previously enabled. 2.7 receive serial input to parallel output (sipo) during sts-12/stm-4 operation, the sipo is used to convert the 622.08 mbps serial data input to 77.76 mbps parallel data output which can interface to a sonet framer/asic. if the xrt91l30 is operating in sts-3/ stm-1, the sipo will convert the 155.52 mbps serial data input to 19.44 mbps parallel data output. the sipo f igure 7. los d eclaration circuit internal los detect dlosdis losext ( sd ) los declaration
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 18 bit de-interleaves the serial data input into an 8-bit parallel output to rxdo[7:0]. a simplified block diagram is shown in figure 8 . xrt91l30 clocks data out on rxdo[7:0] at the falling edge of rxpclko. 2.8 receive parallel output interface the 8-bit single-ended lvttl running at 77.76 mbps (sts-12/stm-4) or 19.44 mbps (sts-3/stm-1) parallel data output of the receive path is used to interface to a sonet framer/asic synchronized to the recovered clock. a simplified block diagram is shown in figure 9 . 2.9 disable parallel receive data output upon los the parallel receiver outputs are automatically pulled "low" or forced to a logic state of "0" during a los condition to prevent data chattering unless los detection is disabled by asserting dlosdis and keeping losext input pin "high." in addition, the user can also assert losext input pin "low" from the optical module to force an los and mute the parallel receiver outputs as well (while dlosdis input is also low, see figure 7 ). f igure 8. s implified b lock d iagram of sipo f igure 9. r eceive p arallel o utput i nterface b lock b 0 0 b 0 1 b 0 2 b 0 3 b n 0 b n 1 b n 2 b n 3 b n+ 0 b n+ 1 b n+ 2 b n+ 3 b 7 0 b 7 1 b 7 2 b 7 3 8-bit parallel lvttl output data rxdo0 rxdo7 rxdo n+ rxdo n rxip/n rxpclko b 3 0b 2 0b 1 0b 0 0 b 7 0b 6 0b 5 0b 4 0 b 3 3b 2 3b 1 3 b 4 3 b 5 3 b 6 3 b 7 3 sipo 77.76 mhz (sts-12/stm-4) or 19.44 mhz (sts-3/stm-1) 622.08 mbps sts-12/stm-4 or 155.52 mbps sts-3/stm-1 serial data rate sonet framer/asic xrt91l30 sts-12/stm-4 or sts-3/stm-1 transceiver rxpclko rxdo[7:0] 8
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 19 2.10 receive parallel data output timing the receive parallel data output from the sts-12/stm-4 or sts-3/stm-1 receiver will adhere to the setup and hold times shown in figure 10 , table 7 , and ta b l e 8 . table 9 shows the pecl and ttl output timing specifications. f igure 10. r eceive p arallel o utput t iming t able 7: r eceive p arallel d ata o utput t iming (sts-12/stm-4 o peration ) t able 8: r eceive p arallel d ata o utput t iming (sts-3/stm-1 o peration ) s ymbol p arameter m in t yp m ax u nits t rxclk receive high-speed serial clock period 1.608 ns t rxpclko receive parallel data output byte clock period 12.86 ns t rxdo_valid time the data is valid on rxdo[7:0] and framepulse before and after the rising edge of rxpclko 4 ns t pulse_wid pulse width of frame detection pulse on framepulse 12.86 ns s ymbol p arameter m in t yp m ax u nits t rxclk receive high-speed serial clock period 6.43 ns t rxpclko receive parallel data output byte clock period 51.44 ns t rxdo_valid time the data is valid on rxdo[7:0] and framepulse before and after the rising edge of rxpclko 22 ns t pulse_wid pulse width of frame detection pulse on framepulse 51.44 ns t rxclk rxpclko rxdo[7:0] rxip rxin framepulse t rxdo_valid t rxpclko a1 a2 a2 a2 a2 t pulse_wid
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 20 t able 9: pecl and ttl r eceive o utputs t iming s pecification s ymbol p arameter m in t yp m ax u nits t r_pecl pecl output rise time (20% to 80%) 350 ps t f_pecl pecl output fall time (80% to 20%) 350 ps t r_ttl ttl output rise time (10% to 90%) 2 ns t f_ttl ttl output fall time (90% to 10%) 1.5 ns
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 21 3.0 transmit section the transmit section of the xrt91l30 accepts 8-bit parallel data and converts it to serial differential lvpecl data output intented to interface to an optical module. it consists of an 8-bit parallel single-ended lvttl interface, parallel-to-serial converter, a clock multiplier unit (cmu), a low voltage positive-referenced emitter- coupled logic (lvpecl) differential line driver, and loop timing modes. the lvpecl serial data output rate is 622.08 mbps for sts-12/stm-4 applications and 155.52 mbps for sts-3/stm-1 applications. the high frequency serial clock is synthesized by a pll, which uses a low frequency clock as its input reference. in order to synchronize the data transfer process, the synthesized 622.08 mhz for sts-12/stm-4 or 155.52 mhz sts-3/stm-1 serial clock output is divided by eight and the 77.76 mhz (sts-12/stm-4) or 19.44 mhz (sts-3/ stm-1) clock respectively is presented to the framer/mapper device to be used as its timing source. 3.1 transmit parallel input interface the parallel data from an framer/mapper device is presented to the xrt91l30 through an 8-bit single-ended lvttl parallel bus interface txdi[7:0]. to directly interface to the xrt91l30, the sonet framer/asic must be synchronized to the same timing source txpclk_io in presenting data on the parallel bus interface. the data must meet setup and hold times with respect to txpclk_io. this clock output source is used to synchronize the sonet framer/asic to the xrt91l30. the framer/mapper device should use txpclk_io as its timing source so that parallel data is phase aligned with the serial transmit data. the data is latched into a parallel input register on the rising edge of txpclk_io. txpclk_io is derived from a divide-by-8 of the high speed synthesized clock resulting in a 77.76/ 19.44 mhz single-ended lvttl clock output source to be used by the framer/mapper device for parallel bus synchronization. a simplified block diagram of the transmit parallel bus clock output system interface is shown in figure 11 . f igure 11. t ransmit p arallel i nput i nterface b lock sonet framer/asic refclkp txpclk_io ttlrefclk xrt91l30 sts-12/stm-4 or sts-3/stm-1 transceiver txdi[7:0] 8 cmufreqsel refclkn pio_ctrl vdd+
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 22 3.2 transmit parallel data input timing when applying parallel data input to the transmitter, the setup and hold times should be followed as shown in figure 12 and ta b l e 10 , table 11 . f igure 12. t ransmit p arallel i nput t iming t able 10: t ransmit p arallel d ata i nput t iming (sts-12/stm-4 o peration ) t able 11: t ransmit p arallel d ata i nput t iming (sts-3/stm-1 o peration ). s ymbol p arameter m in t yp m ax u nits t txpclk_io transmit clock output period 12.86 ns t txdi_su transmit data setup time with respect to txpclk_io 2.0 ns t txdi_hd transmit data hold time with respect to txpclk_io 1.0 ns s ymbol p arameter m in t yp m ax u nits t txpclk_io transmit clock output period a a. 51.44 ns t txdi_su transmit data setup time with respect to txpclk_io 2.0 ns t txdi_hd transmit data hold time with respect to txpclk_io 1.0 ns t txpclk_io txdi[7:0] txpclk_io t txdi_hd t txdi_su transmit parallel clock output transmit parallel clock driven by xrt91l30 device
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 23 3.3 alternate transmit parallel bus clock input option to decouple transmit parallel clock domains of the framer/mapper device and the xrt91l30 transceiver and to eliminate difficult timing issues between them, the transmit parallel clock txpclk_io can also be optionally configured as a clock input. rather than provide a transmit parallel clock output reference to the framer/mapper device, the xrt91l30 can instead accept a reference transmit parallel clock input signal from the framer/ mapper device to sample the transmit parallel bus. when pio_ctrl pin 48 is asserted "low," txpclk_io switches into a clock input and the xrt91l30 will now sample data on the transmit parallel bus txdi[7:0] based on txpclk_io clock input reference coming from the framer/mapper device. the use of the alternate transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing. figure 13 provides a detailed overview of the alternate transmit parallel bus clock input system interface. 3.4 alternate transmit parallel data input timing when applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of operation, the setup and hold times should be followed as shown in figure 14 and table 12 , table 13 . f igure 14. a lternate t ransmit p arallel i nput t iming f igure 13. a lternate t ransmit p arallel i nput i nterface b lock (p arallel c lock i nput o ption ) sonet framer/asic txpclk_io xrt91l30 sts-12/stm-4 or sts-3/stm-1 transceiver txdi[7:0] 8 (parallel clock input option) refclkp ttlrefclk cmufreqse l refclkn pio_ctrl t txpclk_io txdi[7:0] txpclk_io t txdi_hd t txdi_su alternate transmit parallel clock input option transmit parallel clock driven by framer/mapper device
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 24 t able 12: a lternate t ransmit p arallel d ata i nput t iming (sts-12/stm-4 o peration ) t able 13: a lternate t ransmit p arallel d ata i nput t iming (sts-3/stm-1 o peration ). 3.5 transmit parallel input to serial output (piso) the piso is used to convert 77.76 mbps or 19.44 mbps parallel data input to 622.08 mbps sts-12/stm-1 or 155.52 mbps sts-3/stm-1 serial data output respectively, which can interface to an optical module. the piso bit interleaves parallel data input into a serial bit stream taking the first bit from txdi7, then the first bit from txdi6, and so on as shown in figure 15 . s ymbol p arameter m in t yp m ax u nits t txpclk_io transmit clock input period 12.86 ns t txdi_su transmit data setup time with respect to txpclk_io 2.0 ns t txdi_hd transmit data hold time with respect to txpclk_io 1.0 ns s ymbol p arameter m in t yp m ax u nits t txpclk_io transmit clock input period 51.44 ns t txdi_su transmit data setup time with respect to txpclk_io 2.0 ns t txdi_hd transmit data hold time with respect to txpclk_io 1.0 ns f igure 15. s implified b lock d iagram of piso b 0 0 b 0 1 b 0 2 b 0 3 b 0 4 b 0 5 b 0 6 b 0 7 b n 0 b n 1 b n 2 b n 3 b n 4 b n 5 b n 6 b n 7 b n+ 0 b n+ 1 b n+ 2 b n+ 3 b n+ 4 b n+ 5 b n+ 6 b n+ 7 b 7 0 b 7 1 b 7 2 b 7 3 b 7 4 b 7 5 b 7 6 b 7 7 8-bit parallel lvttl input data txdi0 txdi7 txdi n+ txdi n txop/ n txpclk_io 77.76 mhz (sts-12/stm-4) or 19.44 mhz (sts-3/stm-1) 622.08 mbps sts-12/stm-4 or 155.52 mbps sts-3/stm-1 serial data rate b 4 0 b 5 0 b 6 0 b 7 0b 2 0 b 3 0b 4 7 b 5 7 b 6 7 b 7 7 b 0 7 b 1 7 b 2 7 b 3 7 piso time (0)
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 25 3.6 clock multiplier unit (cmu) and re-timer the clock synthesizer uses a 77.76 mhz or a 19.44 mhz reference clock to generate the 622.08 mhz (for sts- 12/stm-4) or 155.52 mhz (for sts-3/stm-1) sonet/sdh transmit serial data rate frequency. differential lvpecl input refclkp/n accepts a clock reference of 77.76 mhz or 19.44 mhz to synthesize a high speed 622.08 mhz clock for sts-12/stm-4 or 155.52 mhz clock for sts-3/stm-1 applications. optionally, if a differential lvpecl clock source is not available, ttlrefclk can accept an lvttl clock signal. the clock synthesizer uses a pll to lock-on to the differential input refclkp/n or single-ended input ttlrefclk reference clock. the refclkp/n input should be generated from an lvpecl crystal oscillator which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary accuracy required for sonet systems. if the ttlrefclk reference clock is used, the ttlrefclk reference input should be tied to a lvttl crystal oscillator with 20ppm accuracy. the two reference clocks are xnor?ed and the choice between the lvpecl and lvttl clocks are controlled tying either refclkp or ttlrefclk to ground. ta b l e 1, on page 12 shows the cmu reference clock frequency settings. table 14 specifies the clock multiplier unit?s requirements for the reference clock. t able 14: c lock m ultiplier u nit ? s r equirements for r efclk jitter specification is de fined using a 12khz to 1.3/5mhz lp-hp single-pole filter. 1 these reference clock jitter limits are required for the outputs to meet sonet system level jitter requirements (<10 mui rms ). 2 required to meet sonet output frequency stability requirements. 3.7 loop timing and clock control two types of loop timing are possible in the xrt91l30. in the internal loop timing mode, loop timing is controlled by the looptime pin. this mode is selected by asserting the looptime signal to a high level. when the loop timing mode is activated, the cmu synthesized hi-speed reference clock input to the retimer is replaced with the hi-speed internally recovered receive clock coming from the cdr. under this condition both the tr ansmit and receive sections are synchronized to the internally recovered receive clock. loop time mode directly locks the retimer to the recovered receive clock. in external loop timing mode, the xrt91l30 allows the user the flexibility of using an externally recovered receive clock for retiming the high speed serial data. first, the cdrdis input pin should be set high. by doing so, the internal cdr is disabled and bypassed and the xrt91l30 will sample the incoming high speed serial data on rxip/n with the externally recovered receive clock connected to the xrxclkip/n inputs. in this state, the receive clock de-jittering and recovery is done externally and fed thru xrxclkip/n and the xrt91l30 will sample rxip/n on the rising edge of xrxclkip/n. secondly, the looptime pin must also be set high in order to select the externally recovered receive clock on xrxclkip/n as the reference clock source for the transmit serial data output stream txop/n. n ame p arameter m in t yp m ax u nits ref duty reference clock duty cycle 40 60 % ref jit reference clock jitter (rms) with 19.44 mhz reference 1 5 ps ref jit reference clock jitter (rms) with 77.76 mhz reference 1 13 ps ref tol reference clock frequency tolerance 2 -20 +20 ppm
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 26 ta b l e 15 provides configuration for selecting the loop timing and clock recovery modes. the use of the on-chip cdr or an external recovered clock in loop timing applications is shown in figure 16 . t able 15: l oop t iming and c lock r ecovery configurations cdrdis looptime t ransmit c lock s ource r eceive c lock s ource 0 0 clock multiplier unit cdr enabled. clock and data recovery by internal cdr 0 1 internal cdr cdr enabled. clock and data recovery by internal cdr 1 0 clock multiplier unit cdr disabled. externally recovered receive clock from xrxclkip/n 622.08/155.52 mbps data on rxip/n sampled at rising edge of xrxclkip/n 1 1 external cdr thru xrxclkip/n cdr disabled. externally recovered receive clock from xrxclkip/n 622.08/155.52 mbps data on rxip/n sampled at rising edge of xrxclkip/n f igure 16. l oop t iming m ode u sing i nternal cdr or an e xternal r ecovered c lock rxip rxin mux cdr mux mux refclkp refclkn ttlrefclk cdrdis div by 8 clk data ~ ~ ~ ~ xrt91l30 looptime xrxclkip xrxclkin data piso to retimer sipo retimer txop txon clk 8 rxdo[7:0] rxpclko data clk txpclk_io pio_ctrl enb enb mux 0 1 div by 8 8 txdi[7:0] 622.08/ 155.52mhz cmu
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 27 3.8 transmit serial output control the 622.08 mbps sts-12/stm-4 or 155.52 mbps sts-3/stm-1 transmit serial output is avaliable on txop/n pins. the transmit serial output can be ac or dc coupled to an optical module or electrical interface. a simplified dc coupling block diagram is shown in figure 17 . n ote : some optical modules integrate ac coupling capacitors within the module. ac or dc coupling is largely specific to system design and optical module of choice. f igure 17. t ransmit s erial o utput i nterface block optical module txop txon optical fibe r xrt91l30 sts-12/stm-4 or sts-3/stm-1 transceiver 120 82 install terminators as close to optical module transmit pins vdd
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 28 4.0 diagnostic features 4.1 serial remote loopback the serial remote loopback function is activated by setting rloops "high". when serial remote loopback is activated, the high-speed serial receive data from rxip/n is presented at the high speed transmit output txop/n, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input of the retimer. during serial remote loopback, the high-speed receive data (rxip/n) is also converted to parallel data and presented at the low-speed receive parallel interface rxdo[7:0]. the recovered receive clock is also divided by 8 and presented at the low-speed clock output rxpclko to synchronize the transfer of the 8-bit received parallel data. a simplified block diagram of serial remote loopback is shown in figure 18 . 4.2 digital local loopback the digital local loopback is activated when the dloop signal is set "high." when digital local loopback is activated, the high-speed data from the output of the parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to parallel converter. the cmu output is also looped back to the receive section and is used to synchronize the transfer of the data through the receiver. in digital loopback mode, the transmit data from the transmit parallel interface txdi[7:0] is serialized and presented to the high- speed transmit output txop/n using the high-speed 622.08/155.52 mhz transmit clock generated from the clock multiplier unit and presented to the input of the retimer and sipo. a simplified block diagram of digital loopback is shown in figure 19 . receive data mute upon los, as shown in figure 7 , applies to digital local loopback mode. f igure 18. s erial r emote l oopback f igure 19. d igital l ocal l oopback piso re-timer lvpecl output drivers lvpecl input drivers cdr sipo r x parallel output tx serial outpu t serial remote loopback rx serial inpu t piso re-timer lvpecl output drivers lvpecl input drivers cdr sipo r x parallel output tx serial outpu t digital loopback tx parallel input
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 29 4.3 analog local loopback analog local loopback (aloop) controls a more comprehensive version of digital local loopback in which the point where the transmit data is looped back is moved all the way back to the high-speed receive i/o. the transmit data from the transmit parallel interface txdi[7:0] is serialized and presented to the high-speed transmit output txop/n using the high-speed 622.08/155.52 mhz transmit clock generated from the clock multiplier unit. in addition, the high-speed transmit data txop/n is looped back to the receive clock and data recovery unit, replacing the rxip/n. the signal is then processed by the cdr, and is sent through the serial to parallel converter and presented at the low-speed receive parallel interface rxdo[7:0]. aloop is invoked by asserting the aloop pin "high." a simplified block diagram of parallel remote loopback is shown in figure 20 . receive data mute upon los, as shown in figure 7 , applies to analog local loopback. 4.4 split loopback the serial remote loopback and the digital local loopback can be combined to form a split loopback. the output of the parallel to serial converter is looped back and presented to the high-speed input of the receiver serial to parallel converter. the high-speed serial receive data from rxip/n is presented at the high speed transmit output txop/n, and the high-speed recovered clock is selected to re-time the high speed transmit data output. a simplified block diagram of parallel remote loopback is shown in figure 21 . f igure 21. s plit l oopback f igure 20. a nalog l ocal l oopback piso re-timer lvpecl output drivers lvpecl input drivers cdr sipo tx parallel input r x parallel output tx serial outpu t analog local loop back piso re-timer lvpecl output drivers lvpecl input drivers cdr sipo tx parallel input r x parallel output tx serial outpu t split loopback rx serial inpu t
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 30 4.5 eye diagram the xrt91l30 eye diagram illustrates the transmit serial output signal integrity and quality. 4.6 sonet jitter requirements sonet equipment jitter requirements are specified for the following types of jitter. the definitions of each of these types of jitter are given below. sonet equipment jitter requirements are specified for the following two types of jitter. 4.6.1 jitter tolerance: jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input oc-n equipment interface that causes an equivalent 1db optical power penalty. oc-1/sts-1, oc-3/sts-3, oc-12 and oc-48 category ii sonet interfaces should tolerate, the input jitter applied according to the mask of figure 23 , with the corresponding parameters specified in the figure. f igure 22. t ransmit e lectrical o utput e ye d iagram sts-3/stm-1 sts-12/stm-4
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 31 f igure 23. gr-253 j itter t olerance m ask t able 16: xrt91l30 r eceiver j itter t olerance p erformance i nterface f requency b and i nterval gr-253/ g.783 m inimum p ermissible l imit xrt91l30 j itter t olerance l ow h igh m inimum t ypical m aximum o ptical (kh z ) (mh z ) ui p2p ui p2p ui p2p ui p2p oc3/stm1 65 1 0.15 0.4 oc12/stm4 250 5 0.15 0.4 f igure 24. xrt91l30 m easured j itter t olerance with 77.76mh z r eference c lock sts-3/stm-1 sts-12/stm-4 oc-n/sts-n level 1 3 12 48 f0 (hz) 10 10 10 10 f1 (hz) 30 30 30 600 f2 (hz) 300 300 300 6000 f3 (hz) 2k 6.5k 25k 100k f4 (hz) 20k 65k 250k 1000k a1 (uipp) 0.15 0.15 0.15 0.15 a2 (uipp) 1.5 1.5 1.5 1.5 a3 (uipp) 15 15 15 15 input jitter amplitude (ui pp ) a 3 a 2 a 1 f 0 f 1 f 2 f 3 f 4 slope= -20db/decade slope= -20db/decade jitter frequency (hz) 3 12 10 10 30 30 300 300 6.5k 25k 65k 250k 0.15 0.15 1.5 1.5 15 15
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 32 4.6.2 jitter generation jitter generation is defined as the amount of jitter at the sts-n output in the absence of applied input jitter. the bandwidth is set according to the data rate. the bellcore and itu requirement for this type jitter is 0.01ui rms measured with a specific band-pass filter. for more information on these specifications refer to bellcore tr-nwt-000253 sections 5.6.2-5 and gr-253- core section 5.6 and itut g.783 section 9.3.1.1. ta b le 17 below shows the jitter generation limits per bellcore gr-253 and itut g.783 versus xrt91l30 typical jitter performance. f igure 25. xrt91l30 m easured j itter t olerance with 19.44mh z r eference c lock sts-3/stm-1 sts-12/stm-4 t able 17: xrt91l30 o ptical j itter g eneration using 2 23 -1 prbs pattern i nterface m easurement b and f ilter -3db f requencies gr-253/ g.783 m aximum p ermissible l imit xrt91l30 i ntrinsic j itter (t ransmit p arallel c lock i nput d irection ) xrt91l30 i ntrinsic j itter (t ransmit p arallel c lock o utput d irection ) h igh p ass l ow p ass 19.44 mh z r ef c lock 77.76 mh z r ef c lock 19.44 mh z r ef c lock 77.76 mh z r ef c lock o ptical (kh z ) (mh z ) mui rms mui rms mui rms mui rms mui rms oc3/stm1 12 1.3 10 2 1 2 oc12/stm4 12 5 10 7 8 7 t able 18: xrt91l30 o ptical j itter g eneration using 2 23 -1 prbs pattern using alternate standard f ilters i nterface m easurement b and f ilter -3db f requencies xrt91l30 i ntrinsic j itter (t ransmit p arallel c lock i nput d irection ) xrt91l30 i ntrinsic j itter (t ransmit p arallel c lock o utput d irection ) h igh p ass l ow p ass 19.44 mh z r ef c lock 77.76 mh z r ef c lock 19.44 mh z r ef c lock 77.76 mh z r ef c lock o ptical (kh z ) (mh z ) mui rms mui rms mui rms mui rms oc3/stm1 65 1.3 2 1 2 oc12/stm4 250 a a. according to itu-t g.783 5 4 5 4
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 33 5.0 electrical characteristics absolute maximum ratings n ote : stresses listed under absolute maximum power and i/o ratings may be applied to devices one at a time without causing permanent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods will severely affect device reliability. thermal resistance of qfp package........ ja = 45 c/w operating temperature range.................-40c to 85c thermal resistance of qfp package........ jc = 12 c/w case temperature under bias..................-55c to 125c esd protection (hbm)..........................................>2000v storage temperature ...............................-65c to 150c absolute maximum power and input/output ratings s ymbol t ype p arameter m in . t yp . m ax . u nits vdd 3.3 cmos digital power supply -0.5 6.0 v vdd lvpecl pecl i/o power supply -0.5 6.0 v avdd _io 3.3v analog i/o and power supply -0.5 6.0 v lvpecl dc logic signal input voltage -0.5 vdd lvpecl +0.5 v lvttl dc logic signal input voltage -0.5 5.5 v lvttl dc logic signal output voltage -0.5 vdd 3.3 +0.5 v lvpecl input current -100 100 ma lvttl input current -100 100 ma power and current dc electrical characteristics test conditions: vdd = 3.3v + 5% unless otherwise specified s ymbol t ype p arameter m in . t yp . m ax . u nits c onditions vdd 3.3 power supply voltage 3.135 3.3 3.465 v avdd 3.3 transmit power supply voltage (avdd3.3_tx) 3.135 3.3 3.465 v avdd 3.3 receiver power supply voltage (avdd3.3_rx) 3.135 3.3 3.465 v vdd lvpecl pecl i/o power supply voltage 3.135 3.3 3.465 v i dd-oc3 total power supply current 200 ma i dd-oc12 total power supply current 242 ma p dd-oc3 total power consumption 660 mw p dd-oc12 total power consumption 800 mw
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 34 lvpecl and lvttl logic signal dc electrical characteristics n ote : all input control pins are lvcmos and lvttl compatible. all output control pins are lvcmos compatible and lvttl compliant to 1 ma maximum current drive. test conditions: vdd = 3.3v + 5% unless otherwise specified s ymbol t ype p arameter m in t yp m ax u nits c onditions v oh lvpecl output high voltage vdd lvpecl - 0.9 v v ol lvpecl output low voltage 0.7 v v ocomm lvpecl output common mode voltage 1.1 vdd lvpecl - 1.3 v v odiff lvpecl output differential voltage 600 1300 mv terminate with 50 to vdd lvpecl - 2.0 v ih lvpecl input high voltage vdd lvpecl - 0.9 vdd lvpecl - 0.3 v for single-ended v il lvpecl input low voltage 0 vdd lvpecl - 1.72 v for single-ended v idiff lvpecl input pecl differential voltage 400 1600 mv peak-to-peak v icomm lvpecl input pecl common mode voltage 1.5 - v idiff /2 vdd lvpecl - 1.0 - v idiff /2 v v oh lvttl/ lvcmos output high voltage 2.4 vdd 3.3 v i oh = -1.0ma v ol lvttl/ lvcmos output low voltage 0 0.4 v i ol = 1.0ma v ih lvttl/ lvcmos input high voltage 2.0 vdd 3.3 v v il lvttl/ lvcmos input low voltage 0 0.8 v i ih lvttl/ lvcmos input high current 50 500 a 2.0v xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 35 package dimensions ordering information p art n umber p ackage o perating t emperature r ange xrt91l30iq 64-pin plastic quad flat pack (10.0 x 10.0 x 2.0 mm, qfp) -40 c to +85 c x rt91l3 0 symbol min max min max a 0.072 0.096 1.82 2.45 a1 0.010 0.020 0.25 0.50 a2 0.071 0.087 1.80 2.20 b 0.007 0.011 0.17 0.27 c 0.004 0.009 0.11 0.23 d 0.510 0.530 12.95 13.45 d1 0.390 0.398 9.90 10.10 e 0.0197 bsc 0.50 bsc l 0.029 0.041 0.73 1.03 0 7 0 7 inches millimeters note: the control dimension is in millimeters.
xrt91l30 xr sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver rev. 1.0.1 36 revision history r evision # d ate d escription 1.0.1 december 2006 xrt91l30 datasheet.
xr xrt91l30 rev. 1.0.1 sts-12/stm-4 or sts-3/stm-1 sonet/sdh transceiver 37 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet november 2006. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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